`timescale 1ns/1ps
module adff_tb (
    
);

reg clk,rstn,d;
wire q;
adff adff(
     .clk(clk)
    ,.rstn(rstn)
    ,.d(d)
    ,.q(q)
);

initial begin
   clk = 1'b0;
   rstn = 1'b0;
   d = 1'b0;
   forever begin
     #10 clk = ~clk;
   end
 end

always  begin
    #12 d = 1'b1;
    #2 rstn = 1'b1;
    #13 d = 1'b0;
    #16 d = 1'b1;
    #7 d = 1'b0;
    #13 d = 1'b1;
    #17 d = 1'b0;
end
endmodule //adff_tb